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Operational Phases and Modes of Operation
4.5
Power control modes of operation
The Version 1 ColdFire architecture incorporates several modes of operation. These include Reset, Run,
Stop and Halt (debug). ? A , ? I and Sleep phases in Figure 4-6 are all mapped into the ColdFire STOP mode
on this device. The CPU has only a single view of STOP operation, but at the device level, additional levels
of distinction have been added:
STOP FC
STOP SC
STOP NC
STOP – Clock in Fast Mode. Nominally used for ? A .
STOP – Clock in Low Speed Mode. Nominally used for ? I .
STOP – All clocks disabled. Nominally used for the SLEEP phase.
Boot and ? D are functionally identical and map into the Run mode. Figure 4-7 adds HALT mode to the
summarizes the triggers that cause transitions from one mode to the next.
RESET can be entered from any mode.
1
STOP SC
?? I )
RUN
?? D & Boot)
2
7
4
3
STOP FC
?? A )
9
5
8
RESET
6
STOP NC
(SLEEP)
HALT
Figure 4-7. Allowable state transitions
Table 4-2. State transitions
Transition #
1
From
RUN
STOP SC
To
STOP SC
RUN
Trigger 1
XCSR[ENBDM] = 0, STOPCR[SC] = 1; followed by STOP instruction
Any interrupt
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
42
Freescale Semiconductor, Inc.
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